Asic/Soc Functional Design Verification: A Comprehensive Guide to Technologies and Methodologies
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Book Overview
This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon. The author first outlines all of the verification sub-fields at a high level, with just enough depth to allow an engineer to grasp the field before delving into its detail. He then describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, ReuseMethodology from Algorithm/ESL to RTL, and other overall methodologies.
Format:Paperback
Language:English
ISBN:3319866206
ISBN13:9783319866208
Release Date:August 2018
Publisher:Springer
Length:328 Pages
Weight:1.12 lbs.
Dimensions:0.8" x 6.1" x 9.2"
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