Modeling the performance of a field effect transistor having a dynamically depleted channel region: United States Patent 9996650
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Disclosed are a system, a method and a computer program product for accurately modeling the performance of a body-contacted, asymmetric double gate, dynamically depleted (DD), semiconductor-on-insulator (SOI) field effect transistor (FET). This modeling can be performed, using iterative processing, to determine the conditions (e.g., back gate bias voltage, front gate bias voltage, body resistance and body charge) under which the FET channel region transitions from being in a partially depleted (PD) state such that the FET functions as a PD SOI FET to being in a fully depleted (FD) state such that the FET functions as a FD SOI FET. Once these conditions are known (i.e., once the model is generated), the DD SOI FET can be incorporated into top-level integrated circuit designs with specifications that either meet the conditions or do not meet the conditions, depending upon the desired function of the DD SOI FET within the integrated circuit.
Format:Paperback
Language:English
ISBN:B08RGV6VYR
ISBN13:9798585169939
Release Date:January 1
Publisher:Independently Published
Length:28 Pages
Weight:0.20 lbs.
Dimensions:0.1" x 8.5" x 11.0"
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